The invention relates to phase-locked loop type clock-signal generators that produce a high-frequency clock signal from a low-frequency clock signal. Among these generators, the invention relates more specifically to those using a digital oscillator producing clock signals whose period is proportional to a binary number received by the oscillator.
A prior art generator 10 of this kind, as illustrated in FIG. 1, has a comparator 12 and a digital oscillator 20 connected in series. An output OUT of the oscillator 20 is connected to an input of the comparator 12. The generator 10 gives a high-frequency signal CKHF (with a period PHF) from a low-frequency reference signal CKBF (with a period PBF).
The comparator 12 has two inputs to which the high-frequency signal CKHF and the low-frequency reference signal CKBF are applied. The comparator 12 compares the period PHF of the high-frequency signal CKHF with a desired period PHF0. The desired period is, for example, a multiple of the period PBF. The comparator 12 produces a number NR of N0 bits having the following characteristics: NR increases if PHF less than PHF0, NR decreases if PHF greater than PHF0, otherwise NR is constant.
The comparator 12 produces the number NR, at N serial outputs, in the form of binary clock signals S(1) to S(N) representing the number NR. In the example of FIGS. 1 and 2, N=2N0 and the signals S(1) to S(N) indicate the value of the number NR: S(NR+1)=1, and S(i)=0 for all values of i ranging from 1 to N and ixe2x89xa0NR+1. In another example, N=N0 and the signals S(1) to S(N) correspond to N bits of the number NR.
The digital comparator 20 receives the binary signals S(1) to S(N) and produces the clock signal CKHF at the output OUT. It conventionally includes an odd number of inverters serially connected to form a chain. The period of the signal CKHF obtained depends primarily on the number of inverters and the propagation time of a 0 and a 1 in each inverter.
An exemplary oscillator 20 is shown in FIG. 2. It has N cells C(1) to C(N) each comprising two inputs a, b and two outputs c, d. The N cells are series connected. The inputs a, b of the cells C(1) to C(Nxe2x88x921) are connected to the outputs c, d of the cells C(2) to C(N). The outputs c, d of the cell C(1) are connected together and form the output OUT of the oscillator 20. The switches INTC(1) to INTC(N) are connected between the inputs a, b of each cell C(1) to C(N). The switches INTC(1) to INTC(N) are controlled by the signals S(1) to S(N). They are closed when the signals S(1) to S(N) are active.
The cells C(2) to C(N) are identical. Each cell has an even number NC of inverters series connected between the input and the output c and/or between the input b and the output d. Time periods TC0, TC1, possibly different from one another, are needed to propagate a 0 and a 1 respectively in all the elements of a cell C(2) to C(N), especially all the inverters.
The cell C(1) has a number NCxe2x80x2 of inverters series connected between the input a and the output b and/or the input c and the output d of the cell C(1). The number NCxe2x80x2 is an odd number to obtain the oscillations of the chain of inverters. Time periods TC0xe2x80x2, TC1xe2x80x2, possibly different from one another, are needed to propagate a 0 and a 1 respectively in all the elements of the cell C(1), especially all the inverters.
The clock-signal generator 10 operates as follows. The comparator gives a number NR0 ranging from 0 to 2N0xe2x88x921 in the form of the corresponding signals S(1) to S(N). In the example of FIGS. 1 and 2, S(NR0+1)=1 and S(i)=0 for i ranging from 1 to N, and ixe2x89xa0NR0+1. The switches INTC(1) to INTC(N) open and close as a function of the signals S(1) to S(N). The cells C(NR0+2) to C(N) are isolated and the cells C(1) to C(NR0+1) form a chain comprising an add total number of series connected inverters.
The propagation time of a 0 or a 1 between the cell C(NR0+1) and the cell C(1) depends on the propagation time in each cell. The oscillator 20 gives a signal CKHF at its output OUT. The period of this signal CKHF is equal to PHF=(TC0+TC1)*NR+(TC0xe2x80x2+TC1xe2x80x2) if the propagation time in the switch INTC(NR0+1) is overlooked. The period PHF is therefore proportional to the number NR given by the comparator.
If the period PHF of the clock signal CKHF obtained is smaller than the period desired PHF0, then the comparator increases the number NR to increase the number of cells in the chain, and thus increase the period of the signal CKHF. Conversely, if the period PHF of the signal CKHF obtained is greater than the desired value, then the number NR is reduced to reduce the period of the signal CKHF.
The number NR will thus vary gradually until the desired period PHF0 is reached. The amplitude of the variations of NR is modulated as a function of the difference between the real period PHF of the signal CKHF and the desired period. Thus, when the generator 10 starts working, the period PHF is small, far smaller than PHF0 and the comparator will vary the number NR substantially (+10, +50, +100 if necessary) to greatly increase the period PHF. Conversely, when PHF is close to PHF0, the number NR varies in smaller proportions (+1, xe2x88x921) to obtain PHF=PHF0.
When NR increases or decreases by 1 respectively, a cell C is added or eliminated respectively in the chain. The minimum variation of the period in the oscillator is therefore equal to TC0+TC1, namely to the sum of the propagation times of a 0 and of a 1 in a cell C. The uncertainty over the period that defines the precision of the oscillator 20 is equal to P0=TC0+TC1.
The precision of the oscillator thus depends on the propagation times TC0, TC1 in the cells C(2) to C(N), namely the number of inverters NC contained in these cells and the switching times t0, t1 of these inverters. To improve the precision of the oscillator, it is possible to limit the number of inverters in a cell to NC=2 (the minimum) and/or to reduce the switching times of the inverters.
An inverter generally includes a P-type transistor and an N-type transistor that are series connected. The source of the P-type transistor is connected to a supply VDD and the source of the N-type transistor is connected to ground of the circuit. The gates of the transistors are connected together and form the input of the inverter. The drains of the transistors are connected together and form the output of the inverter.
The switching time of an inverter of this kind is proportional to L2, with L being the length of the gate of the transistors. To reduce the switching times, it is necessary to reduce the gate length L of the transistors. However, the gate length L of the transistors cannot be reduced beyond a minimum length Lmin which depends on the technology chosen to make the integrated circuit. Beyond this limit Lmin, it is no longer possible to make the transistors. The switching time t0, t1 of the inverters therefore cannot be reduced beyond the minimum value t0 min, t1 min.
Consequently, the propagation times TC0, TC1 in the cells C(2) to C(N) are themselves limited by these minimum values. This approach is therefore not sufficient especially if it is required that the uncertainty with regard to the period of the signal CKHF obtained should be very low, for example 1%. The term uncertainty must be understood to mean the maximum variation in period of the signal CKHF when the number NR varies by 1.
In view of the foregoing background, an object of the invention is to provide an oscillator that is different and, in particular, precise, and to provide a clock-signal generator that uses this oscillator. The generator of the invention provides clock signals CKHF with a frequency of about 50 MHZ from a signal with a frequency of about 1 KHz, with an uncertainty of less than 1%.
The invention also relates to a generator comprising an oscillator producing a clock signal from an N-bit control number, with N being an integer greater than 1.
These and other objects, advantages and features according to the invention are provided by an oscillator comprising a first group of cells, and a second group of cells. Each cell in the first group of cells comprises at least one series connected inverter, and first selection means to select a variable number of cells of the first group of cells as a function of NH0 most significant bits of the control number. Each cell in the second group of cells comprises at least one series connected inverter and second selection means to select one of the cells of the second group of cells as a function of NL0 least significant bits of the control number. The cells of the first group and the cells of the second group are series connected to form a chain of inverters.
According to a preferred embodiment, each cell of the second group of cells is assigned a place value j ranging from 1 to NL, with NL being an integer from 1 to N. The second selection means comprises NL switches controlled by signals representing NL0 least significant bits of the control number. Each switch with a place value j is series connected with a cell having the same place value j belonging to the second group of cells between an input point and an output point.
Two different cells of the second group of cells have different propagation times for a 0 and a 1. Preferably, the difference between the propagation time of a 0 and a 1 in a cell with a place value j of the second group of cells and that of a cell with a place value jxe2x88x921 is smaller than the relative uncertainty sought for the period of the clock signal obtained.
When the control number increases by 1, a cell with a place value j of the second group is selected. This selected cell is the cell with the place value immediately higher than that of a previously selected cell, or the cell with a lower place value, and an additional cell of the first group of cells in this case is also selected. The period of the clock signal thus follows the variations of the control number.
The generator according to the invention may also comprise a comparator to compare the period of the clock signal with a desired period, and give the control number in the form of N logic signals. The control number varies as follows. The control number increases if the period of the clock signal is smaller than the desired period. The control number decreases if the period of the clock signal is greater than the desired period. Otherwise, the control number is constant. Thus, when the control number increases or decreases respectively, then the period of the clock signal increases and decreases respectively.
According to the preferred embodiment, the generator also has a first decoder to decode the NL0 least significant bits of the control number for providing a first set of NL=2NL0 control signals to the second selection means. These control signals have the following properties. SDL(j)=1 if j=NRL+1 for any value of j ranging from 1 to NL, with NRL corresponding to the decimal value of the NL0 least significant bits of the control number.
The generator may also but not necessarily comprise a second decoder to decode the NH0 most significant bits of the control number, and give the first selection means a second set of NH=2NH0 control signals having the following properties. SDH(i)=1 if i=NRH+1 for any value of i ranging from 1 to NH, with NRH corresponding to the decimal value of the NH0 most significant bits of the control number.
A generator according to the invention may be improved by adding a control circuit to verify the following inequality: 0xe2x89xa6(TC0+TC1)+(TD0(1)+TD1(1))xe2x88x92(TD0(NL)+TD1(NL)). TC0+TC1 is the propagation time of a 0 and a 1 in a cell of the first group of cells. TD0(1)+TD1(1) is the propagation time of a 0 and a 1 in the least significant cell of the second group of cells. TD0(NL)+TD1(NL) is the propagation time of a 0 and a 1 in the most significant cell of the second group of cells. The control circuit produces a control signal if the inequality is not verified, and the comparator increases the control number by one unit when it receives the control signal.
According to one embodiment of the control circuit, it comprises a reference oscillator to produce a clock signal with a reference period proportional to (TC0+TC1)+(TD0(1)+TD1(1)), and a measurement oscillator to produce a clock signal having a measured period proportional to (TD0(NL)+TD1(NL)). A comparison circuit compares the measured period with a reference period, and gives the active control signal if the measured period is smaller than the reference period.